In the last years the increased integration level of several devices on a single chip has allowed the reduction of the production costs and the manufacturability of more compact and complex products.
Reducing dimensions of devices requires even more sophisticated technologies that need to get stable before being used for mass production. Initially, the probability of failures is relatively large and the percentage of functioning devices is small. To increase the yield to stable values for production, a “learning phase” is used in which information on the critical points of the technology are analyzed.
The acquisition of information necessary for learning how to correct the manufacturing process is called “diagnosis”, and its objective includes identifying the causes that generate the failures.
RAMs are ideal devices for testing whether a production process is mature or not. The static RAMs are the denser blocks, therefore their defects can be high, but the regularity of their structure allows associating to the address of the failing cell to the position of the defect in the matrix. With this association a defect in the array is correlated with a precise topologic configuration called a failure pattern and it is possible to easily get information on the structures that are more likely involved in the failure.
Diagnosis of memory devices starts with a test during which the addresses of the failing cells are collected. Then these addresses are elaborated for realizing a map of the failures, which is subsequently analyzed (“bitmap analysis”) for recognizing recurrent failure patterns in a matrix of memory cells.
Approaches to the diagnosis belong to three different categories. The first is based only on the automatic test equipment (ATE). In this method all the tasks are performed by the ATE, from the test pattern generation to the failing addresses collection and bitmap elaboration.
A second approach shares the testing phases between DFT (Design For Testability) integrated test structures, using the so-called BIST (Built-In Self Test) devices, and the ATE (Automatic Test Equipment) devices. In this approach the BIST, integrated with the memory, generates patterns to stimulate the memory, and the ATE elaborates the bitmap that will be analyzed by the test engineer with the designer to identify the fail patterns.
In both these strategies the efficiency of the diagnosis is limited by the need to allocate dedicated resources to follow all these activities, by the large amount of time necessary for collecting data, and for the continuous interaction with the ATE.
The approaches based on the use of the ATE devices allows collection of all information available during the test. Unfortunately, the ATE devices are expensive and imply a bitmap analysis to be carried out by the test engineer and the designer for identifying recurrent failure patterns that take a relatively long time to be completed.
The third method is the so called drop-in approach that includes a test vehicle having the same pad frame of the product and containing sensitive SoC (System on Chip) modules directly accessible by the test equipments for yield monitoring. For instance, the drop-in includes static RAMs, analog blocks and standard cells. Of course, the drop-in usage, besides being silicon area consuming, suffers from the costs of the traditional ATE flow.
In D.Appello, A. Fudoli, V. Tancorre, F. Corno, M. Rebaudengo and M. Sonza Reorda, “A BIST-Based Solution for Diagnosis of Embedded Memories Adopting Image Processing Techniques”, Proceedings of 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT), 2002, and T. J. Bergfeld, D. Niggemeyer and E. M. Rudnick, “Diagnostic Testing of Embedded Memories using BIST”, Design, Automation and Test in Europe (DATE), Proceedings, pp. 305-309, 2000, a method of carrying out a diagnosis for embedded memory devices by using a BIST is disclosed. The memory to be tested is analyzed with a certain algorithm and the addresses of failures is output toward dedicated diagnostic structures. The analysis of the failure pattern is performed successively.
In K. M. Butler, K. Johnson. J. Platt, A. Kinra, and J. Saxena, “Automated Diagnosis in Testing and Failure Analysis”, IEEE Design & Test of Computers, vol. 14, no. 3, pp. 83-89, 1997, a method of performing a diagnosis is disclosed. Addresses of failing memory cells are found implementing appropriate test algorithms by a BIST.
The approach disclosed in D. Niggemeyer and E. Rudnick, “Automatic Generation of Diagnostic March Tests”, IEEE VLSI Test Symposium (VTS), Proceedings, pp. 299-304, 2001, contemplates the use of a BIST capable of performing on-line a set of instructions for carrying out diagnostic tests on SRAMs, and for collecting information on the detected failures. This approach is particularly useful with embedded devices because of the limited hardware resources they require.
Various approaches for the test and diagnosis of embedded SRAM are compared in T. W. Williams and K. P. Parker, “Design for Testability—A Survey”, Proceedings of the IEEE, 71(1), pp. 98-111, 1983, and V. N. Yarmolik, Y. V. Klimets, A. J. van de Goor and S. N. Demidenko, “RAM Diagnostic Tests”, Proceedings of the IEEE International Workshop on Memory Technology, Design and Testing (MTDT), pp. 100-102, 1996. These articles highlight that the approaches based on integrated structures are more advantageous than the approaches based on ATE devices.
In J. Segal, A. Jee, D. Lepeiian and B. Chu, “Using Electrical Bitmap results from Embedded Memory to Enhance Yield”, IEEE Design & Test of Computers, vol. 18, no. 3, pp. 28-29, 2001, the problem of performing a diagnosis of SRAMs by bitmap analysis is discussed. This article shows that the correlation between defects and failure patterns is usually strong.
The documents R. Treuer and V. K. Agarwal, “Built-In Self Diagnosis for Repairable Embedded RAMs”, IEEE Design & Test of Computers, vol. 10, no.2, pp.24-33, 1993, and R. P. Treuer and V. K. Agarwal, “Fault Location Algorithms for Repairable Embedded RAMs”, IEEE International Test Conference (ITC), Proceedings, pp. 825-834, 1993, highlight that a diagnosis of failures even in a repair process of embedded memory devices would be needed.